Re: Can somebody take a peek at this circuit for me?

Discussion in 'Electronic Basics' started by Larry Brasfield, Mar 22, 2005.

  1. "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...
    > "Larry Brasfield" <> wrote in news:%
    > TY%d.35$e%:

    ....
    Regarding circuit shown at:
    https://netfiles.uiuc.edu/mnoone/www/Linearamplifierwithfet.jpg
    [Why the FET dies resolved.]

    > OK then well now I'm just confused - how would you switch a very high
    > voltage signal with a mosfet with a low voltage input?


    To do that in a DC coupled manner with a ground
    referenced load and a ground referenced controller
    normally requires at least 1 more transistor, itself
    having similar HV withstand. The process of getting
    a signal from one voltage range to another is often
    called "translating". A common base amplifier could
    do it for your application.

    And don't call it "switch" when you mean to drive
    the FET so that it has varying transconductance.

    > I thought one of the
    > big ideas of fets was that you could take a small input voltage and switch
    > a large input voltage - but that seems to not be right?


    That has not been contravened here.

    > Thanks,


    You're welcome. I've set followups to sci.electronics.basics
    because this kind of discussion is more topical there.

    --
    --Larry Brasfield
    email:
    Above views may belong only to me.
     
    Larry Brasfield, Mar 22, 2005
    #1
    1. Advertising

  2. "Larry Brasfield" <> wrote in
    news:YiZ%d.45$e%:

    > "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    > news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...
    >> "Larry Brasfield" <> wrote in
    >> news:% TY%d.35$e%:

    > ...
    > Regarding circuit shown at:
    > https://netfiles.uiuc.edu/mnoone/www/Linearamplifierwithfet.jpg
    > [Why the FET dies resolved.]
    >
    >> OK then well now I'm just confused - how would you switch a very high
    >> voltage signal with a mosfet with a low voltage input?

    >
    > To do that in a DC coupled manner with a ground
    > referenced load and a ground referenced controller
    > normally requires at least 1 more transistor, itself
    > having similar HV withstand. The process of getting
    > a signal from one voltage range to another is often
    > called "translating". A common base amplifier could
    > do it for your application.


    Could you reccomend a transistor that would be able to serve this
    function? I've looked before for high voltage transistors and found very
    little.

    > And don't call it "switch" when you mean to drive
    > the FET so that it has varying transconductance.


    Well - actually I meant switch. Switching is the usage of mosfets that
    I'm familiar with, using them to make a linear output is something I'm
    not fully comfortable with just yet. I was asking in general, not about
    the schematic that I posted.

    >> I thought one of the
    >> big ideas of fets was that you could take a small input voltage and
    >> switch a large input voltage - but that seems to not be right?

    >
    > That has not been contravened here.
    >
    >> Thanks,

    >
    > You're welcome. I've set followups to sci.electronics.basics
    > because this kind of discussion is more topical there.


    So - once a high volage transistor is used to drive the gate, what else
    do I need to change to make the circuit work? Best regards,

    -M. Noone
     
    Michael Noone, Mar 22, 2005
    #2
    1. Advertising

  3. "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    news:Xns96217F7D8C823mnooneuiucedu127001@216.196.97.136...
    > "Larry Brasfield" <> wrote in
    > news:YiZ%d.45$e%:
    >> "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    >> news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...

    ....
    >>> OK then well now I'm just confused - how would you switch a very high
    >>> voltage signal with a mosfet with a low voltage input?

    >>
    >> To do that in a DC coupled manner with a ground
    >> referenced load and a ground referenced controller
    >> normally requires at least 1 more transistor, itself
    >> having similar HV withstand. The process of getting
    >> a signal from one voltage range to another is often
    >> called "translating". A common base amplifier could
    >> do it for your application.

    >
    > Could you reccomend a transistor that would be able to serve this
    > function? I've looked before for high voltage transistors and found very
    > little.


    Go to www.onsemi.com and try again.

    >> And don't call it "switch" when you mean to drive
    >> the FET so that it has varying transconductance.

    >
    > Well - actually I meant switch. Switching is the usage of mosfets that
    > I'm familiar with, using them to make a linear output is something I'm
    > not fully comfortable with just yet. I was asking in general, not about
    > the schematic that I posted.


    In the context you used the word, it was inappropriate
    and indicates, to people sharing the same language,
    that you either misconceive the circuit or are not yet
    familiar with what the word really means.

    ....
    > So - once a high volage transistor is used to drive the gate, what else
    > do I need to change to make the circuit work?


    I would use this configuration:

    VCC
    +
    .----)---.
    | |
    .-. .-.
    | | | |
    | | | |
    '-' '-'
    | |
    | |
    o-----||-+
    | ||->
    | ||-+
    | |
    | |
    | o------.OUT
    | | |
    || | | .-.
    .-----||--. |/ | | |
    | || | GND-| | | |
    | | |> | '-'
    ___ | |\| | | | |
    GND-|___|-o--|-\ | ___ | | GND
    | >---o---|___|----o |
    .--|+/ . |
    | |/| | |
    | GND-|<- |
    | |
    ___ | ___ |
    IN -|___|-o---------|___|-----------------'
    (created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

    You can set the resistors associated with the FET to
    control loop gain while setting the emitter resistor
    to limit the max gate drive. The response will tend
    to be stable if you do not set the power amp stage
    gain too high and make the integrator feedback
    network pole in about the same place that the
    power amp stage has its lowest frequency pole.
    It inverts, so if your heart is set on the transfer
    function you posted, you'll need to adjust.

    I still think you need to

    --
    --Larry Brasfield
    email:
    Above views may belong only to me.
     
    Larry Brasfield, Mar 22, 2005
    #3
  4. Larry Brasfield

    John Fields Guest

    On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    <mnoone.uiuc.edu@127.0.0.1> wrote:

    >"Larry Brasfield" <> wrote in
    >news:YiZ%d.45$e%:
    >
    >> "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    >> news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...
    >>> "Larry Brasfield" <> wrote in
    >>> news:% TY%d.35$e%:

    >> ...
    >> Regarding circuit shown at:
    >> https://netfiles.uiuc.edu/mnoone/www/Linearamplifierwithfet.jpg
    >> [Why the FET dies resolved.]
    >>
    >>> OK then well now I'm just confused - how would you switch a very high
    >>> voltage signal with a mosfet with a low voltage input?

    >>
    >> To do that in a DC coupled manner with a ground
    >> referenced load and a ground referenced controller
    >> normally requires at least 1 more transistor, itself
    >> having similar HV withstand. The process of getting
    >> a signal from one voltage range to another is often
    >> called "translating". A common base amplifier could
    >> do it for your application.

    >
    >Could you reccomend a transistor that would be able to serve this
    >function? I've looked before for high voltage transistors and found very
    >little.
    >
    >> And don't call it "switch" when you mean to drive
    >> the FET so that it has varying transconductance.

    >
    >Well - actually I meant switch. Switching is the usage of mosfets that
    >I'm familiar with, using them to make a linear output is something I'm
    >not fully comfortable with just yet. I was asking in general, not about
    >the schematic that I posted.
    >
    >>> I thought one of the
    >>> big ideas of fets was that you could take a small input voltage and
    >>> switch a large input voltage - but that seems to not be right?

    >>
    >> That has not been contravened here.
    >>
    >>> Thanks,

    >>
    >> You're welcome. I've set followups to sci.electronics.basics
    >> because this kind of discussion is more topical there.

    >
    >So - once a high volage transistor is used to drive the gate, what else
    >do I need to change to make the circuit work? Best regards,


    ---

    +400V>--+-----+---D S---+----------+-------->>--+
    | | G | | |
    | | | [ZENER] | |
    [R1] [R2] | |K | |
    | | +-----+ | |
    | | | | |
    | +-----+ | |
    | | | |
    +-------------------+ Vin [R2] |
    | | | | | |
    | D /-|--+ | [RL]
    |K G---< | | |
    [REF] S \+|-------+-----+ |
    | | | | | |
    | | | [R3] [C1] |
    | | | | | |
    GND>----+-----------+-------+--------+-----+-->>--+


    Use a little high-voltage FET to drive the big FET's gate. They're
    cheap and it doesn't take much (damn near nothing) to drive them. Use
    a micropower opamp and you can get its supply voltage from a resistor
    and a low-current shunt reference tied to the 400V rail (or even just
    a resistive divider) The Zener is to make sure the big MOSFET's gate
    voltage never goes higher than it's supposed to, WRT to the source,
    R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    oscillating.

    --
    John Fields
     
    John Fields, Mar 22, 2005
    #4
  5. "John Fields" <> wrote in message
    news:...
    > On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    > <mnoone.uiuc.edu@127.0.0.1> wrote:

    ....
    > +400V>--+-----+---D S---+----------+-------->>--+
    > | | G | | |
    > | | | [ZENER] | |
    > [R1] [R2] | |K | |
    > | | +-----+ | |
    > | | | | |
    > | +-----+ | |
    > | | | |
    > +-------------------+ Vin [R2] |
    > | | | | | |
    > | D /-|--+ | [RL]
    > |K G---< | | |
    > [REF] S \+|-------+-----+ |
    > | | | | | |
    > | | | [R3] [C1] |
    > | | | | | |
    > GND>----+-----------+-------+--------+-----+-->>--+
    >
    >
    > Use a little high-voltage FET to drive the big FET's gate. They're
    > cheap and it doesn't take much (damn near nothing) to drive them. Use
    > a micropower opamp and you can get its supply voltage from a resistor
    > and a low-current shunt reference tied to the 400V rail (or even just
    > a resistive divider) The Zener is to make sure the big MOSFET's gate
    > voltage never goes higher than it's supposed to, WRT to the source,
    > R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    > oscillating.


    It cannot oscillate no matter what value you use for C1.
    Study it carefully and I'm sure you can see why.

    --
    --Larry Brasfield
    email:
    Above views may belong only to me.
     
    Larry Brasfield, Mar 22, 2005
    #5
  6. "John Fields" <> wrote in message
    news:...
    > +400V>--+-----+---D S---+----------+-------->>--+
    > | | G | | |
    > | | | [ZENER] | |
    > [R1] [R2] | |K | |
    > | | +-----+ | |
    > | | | | |
    > | +-----+ | |
    > | | | |
    > +-------------------+ Vin [R2] |
    > | | | | | |
    > | D /-|--+ | [RL]
    > |K G---< | | |
    > [REF] S \+|-------+-----+ |
    > | | | | | |
    > | | | [R3] [C1] |
    > | | | | | |
    > GND>----+-----------+-------+--------+-----+-->>--+
    >
    >
    > Use a little high-voltage FET to drive the big FET's gate. They're
    > cheap and it doesn't take much (damn near nothing) to drive them. Use
    > a micropower opamp and you can get its supply voltage from a resistor
    > and a low-current shunt reference tied to the 400V rail (or even just
    > a resistive divider) The Zener is to make sure the big MOSFET's gate
    > voltage never goes higher than it's supposed to, WRT to the source,
    > R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    > oscillating.


    What do you think the maximum output will be and
    how does that compare with the "requirement"?

    Would you increase C1 until it formed the dominant
    pole in that loop?

    Where do think that would be, considering where the
    the previously dominant pole is (likely to be)?

    How much loop gain variation would you expect to
    see as the operating point changes?

    --
    --Larry Brasfield
    email:
    Above views may belong only to me.
     
    Larry Brasfield, Mar 22, 2005
    #6
  7. "Larry Brasfield" <> wrote in
    news:8D_%d.51$e%:

    > Go to www.onsemi.com and try again.


    OK - well I'm not entirely sure what I should be looking for, so I just
    looked for a high voltage NPN BJT, and found this:
    http://www.onsemi.com/pub/Collateral/MPSA44-D.PDF - Is that what you
    were describing?


    >> So - once a high volage transistor is used to drive the gate, what

    else
    >> do I need to change to make the circuit work?

    >
    > I would use this configuration:
    >
    > VCC
    > +
    > .----)---.
    > | |
    > .-. .-.
    > | | | |
    > | | | |
    > '-' '-'
    > | |
    > | |
    > o-----||-+
    > | ||->
    > | ||-+
    > | |
    > | |
    > | o------.OUT
    > | | |
    > || | | .-.
    > .-----||--. |/ | | |
    > | || | GND-| | | |
    > | | |> | '-'
    > ___ | |\| | | | |
    > GND-|___|-o--|-\ | ___ | | GND
    > | >---o---|___|----o |
    > .--|+/ . |
    > | |/| | |
    > | GND-|<- |
    > | |
    > ___ | ___ |
    > IN -|___|-o---------|___|-----------------'
    > (created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)
    >
    > You can set the resistors associated with the FET to
    > control loop gain while setting the emitter resistor
    > to limit the max gate drive. The response will tend
    > to be stable if you do not set the power amp stage
    > gain too high and make the integrator feedback
    > network pole in about the same place that the
    > power amp stage has its lowest frequency pole.
    > It inverts, so if your heart is set on the transfer
    > function you posted, you'll need to adjust.
    >
    > I still think you need to


    Correct me if I'm completely wrong [I probabaly am :)] - but to me it
    looks like The input could get stuck sinking a decent amount of current.
    The input to this circuit is coming from a very low current (I think
    about 2ma max or so) DAC board, so that needs to be avoided. I guess I'd
    just buffer the input if that is the case - but I thought I should ask
    to be sure.

    Also - I'm having alot of difficulty figuring out what exactly is
    happening in this circuit. To me - it looks like the output from the op-
    amp just goes through a resistor and is then grounded. It's as if the
    output form the op-amp pretty much doesn't do anything at all.
    Similarly, it looks like both the base and the emitter of the transistor
    are grounded, which again seems odd. Maybe I'm misunderstanding the
    circuit? To me it looks like the node connecting the resistor on the
    output of the op-amp and the emitter of the bjt is grounded, but maybe
    I'm wrong?

    Thanks for all your help, and for putting up with all my questions :)

    -Michael
     
    Michael Noone, Mar 22, 2005
    #7
  8. Larry Brasfield

    John Fields Guest

    On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    <> wrote:

    >"John Fields" <> wrote in message
    > news:...
    >> On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    >> <mnoone.uiuc.edu@127.0.0.1> wrote:

    >...
    >> +400V>--+-----+---D S---+----------+-------->>--+
    >> | | G | | |
    >> | | | [ZENER] | |
    >> [R1] [R2] | |K | |
    >> | | +-----+ | |
    >> | | | | |
    >> | +-----+ | |
    >> | | | |
    >> +-------------------+ Vin [R2] |
    >> | | | | | |
    >> | D /-|--+ | [RL]
    >> |K G---< | | |
    >> [REF] S \+|-------+-----+ |
    >> | | | | | |
    >> | | | [R3] [C1] |
    >> | | | | | |
    >> GND>----+-----------+-------+--------+-----+-->>--+
    >>
    >>
    >> Use a little high-voltage FET to drive the big FET's gate. They're
    >> cheap and it doesn't take much (damn near nothing) to drive them. Use
    >> a micropower opamp and you can get its supply voltage from a resistor
    >> and a low-current shunt reference tied to the 400V rail (or even just
    >> a resistive divider) The Zener is to make sure the big MOSFET's gate
    >> voltage never goes higher than it's supposed to, WRT to the source,
    >> R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    >> oscillating.

    >
    >It cannot oscillate no matter what value you use for C1.
    >Study it carefully and I'm sure you can see why.


    ---
    Typical behavior for you. As the erroree, when you find what you
    think is an error, instead of simply stating what you think it is that
    makes it an error, you hold back and try to get some mileage out of it
    by requiring a lot of work to be done by whom you consider to be the
    errorer.

    In this case, good catch, but... the larger C1 becomes, the greater
    the output ripple becomes, until it starts to look like an
    oscillation. The best C1 is no C1, according to bitethedust.asc which
    you can find on abse and which you can run if you've downloaded
    LTSPICE

    --
    John Fields
     
    John Fields, Mar 22, 2005
    #8
  9. "John Fields" <> wrote in message
    news:...
    > On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    > <> wrote:
    >
    >>"John Fields" <> wrote in message
    >> news:...
    >>> On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    >>> <mnoone.uiuc.edu@127.0.0.1> wrote:

    >>...
    >>> +400V>--+-----+---D S---+----------+-------->>--+
    >>> | | G | | |
    >>> | | | [ZENER] | |
    >>> [R1] [R2] | |K | |
    >>> | | +-----+ | |
    >>> | | | | |
    >>> | +-----+ | |
    >>> | | | |
    >>> +-------------------+ Vin [R2] |
    >>> | | | | | |
    >>> | D /-|--+ | [RL]
    >>> |K G---< | | |
    >>> [REF] S \+|-------+-----+ |
    >>> | | | | | |
    >>> | | | [R3] [C1] |
    >>> | | | | | |
    >>> GND>----+-----------+-------+--------+-----+-->>--+
    >>>
    >>>
    >>> Use a little high-voltage FET to drive the big FET's gate. They're
    >>> cheap and it doesn't take much (damn near nothing) to drive them. Use
    >>> a micropower opamp and you can get its supply voltage from a resistor
    >>> and a low-current shunt reference tied to the 400V rail (or even just
    >>> a resistive divider) The Zener is to make sure the big MOSFET's gate
    >>> voltage never goes higher than it's supposed to, WRT to the source,
    >>> R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    >>> oscillating.

    >>
    >>It cannot oscillate no matter what value you use for C1.
    >>Study it carefully and I'm sure you can see why.

    >
    > ---
    > Typical behavior for you. As the erroree, when you find what you
    > think is an error, instead of simply stating what you think it is that
    > makes it an error, you hold back and try to get some mileage out of it
    > by requiring a lot of work to be done by whom you consider to be the
    > errorer.


    The post you quoted is one I canceled a couple of
    minutes after hitting send. I mistakenly read your
    upper MOSFET as a reversed P-channel device,
    assuming, incorrectly, that you intended to produce
    the 400V output first mentioned by the OP. As I
    was reading your schematic, filling in the missing
    polarity, it looked like a bistable latch. And if that
    was what you had drawn, (or meant to draw), it
    would have taken little time to spot it.

    > In this case, good catch, but... the larger C1 becomes, the greater
    > the output ripple becomes, until it starts to look like an
    > oscillation. The best C1 is no C1, according to bitethedust.asc which
    > you can find on abse and which you can run if you've downloaded
    > LTSPICE


    I'm game. It's not showing up on my newserver
    in alt.binaries.schematics.electronic . Can you
    either email it or state what part values and
    transistors you used? Or post, the .asc, which
    is ASCII, so can be pasted into a post.

    I presume your comments apply to my post of
    12:50, where I asked about loop gain shifts
    and dominant poles. Since you elect to not
    answer that, I want to simulate your circuit
    and see for myself.

    Where did the output ripple come from? I can
    see no source for it in your schematic other
    than an oscillation. I'm about 95% confidant
    that it will oscillate until C1 becomes huge.
    The only question is where the limiting occurs.

    --
    --Larry Brasfield
    email:
    Above views may belong only to me.
     
    Larry Brasfield, Mar 22, 2005
    #9
  10. Larry Brasfield

    Genome Guest

    "John Fields" <> wrote in message
    news:...
    > On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    > <> wrote:
    >
    > >"John Fields" <> wrote in message
    > > news:...
    > >> On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    > >> <mnoone.uiuc.edu@127.0.0.1> wrote:

    > >...
    > >> +400V>--+-----+---D S---+----------+-------->>--+
    > >> | | G | | |
    > >> | | | [ZENER] | |
    > >> [R1] [R2] | |K | |
    > >> | | +-----+ | |
    > >> | | | | |
    > >> | +-----+ | |
    > >> | | | |
    > >> +-------------------+ Vin [R2] |
    > >> | | | | | |
    > >> | D /-|--+ | [RL]
    > >> |K G---< | | |
    > >> [REF] S \+|-------+-----+ |
    > >> | | | | | |
    > >> | | | [R3] [C1] |
    > >> | | | | | |
    > >> GND>----+-----------+-------+--------+-----+-->>--+
    > >>
    > >>
    > >> Use a little high-voltage FET to drive the big FET's gate.

    They're
    > >> cheap and it doesn't take much (damn near nothing) to drive them.

    Use
    > >> a micropower opamp and you can get its supply voltage from a

    resistor
    > >> and a low-current shunt reference tied to the 400V rail (or even

    just
    > >> a resistive divider) The Zener is to make sure the big MOSFET's

    gate
    > >> voltage never goes higher than it's supposed to, WRT to the

    source,
    > >> R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    > >> oscillating.

    > >
    > >It cannot oscillate no matter what value you use for C1.
    > >Study it carefully and I'm sure you can see why.

    >
    > ---
    > Typical behavior for you. As the erroree, when you find what you
    > think is an error, instead of simply stating what you think it is

    that
    > makes it an error, you hold back and try to get some mileage out of

    it
    > by requiring a lot of work to be done by whom you consider to be the
    > errorer.
    >
    > In this case, good catch, but... the larger C1 becomes, the greater
    > the output ripple becomes, until it starts to look like an
    > oscillation. The best C1 is no C1, according to bitethedust.asc

    which
    > you can find on abse and which you can run if you've downloaded
    > LTSPICE
    >
    > --
    > John Fields


    John, that is piss poor. Whilst Larry might not have the bananas to
    tell you why he will probably sweat buckets coming up with some
    'reasons'. You have done yourself and Spice a big unfavour.

    DNA
     
    Genome, Mar 23, 2005
    #10
  11. Larry Brasfield

    John Fields Guest

    On Tue, 22 Mar 2005 15:57:07 -0800, "Larry Brasfield"
    <> wrote:

    >"John Fields" <> wrote in message
    > news:...
    >> On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    >> <> wrote:
    >>
    >>>"John Fields" <> wrote in message
    >>> news:...
    >>>> On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    >>>> <mnoone.uiuc.edu@127.0.0.1> wrote:
    >>>...
    >>>> +400V>--+-----+---D S---+----------+-------->>--+
    >>>> | | G | | |
    >>>> | | | [ZENER] | |
    >>>> [R1] [R2] | |K | |
    >>>> | | +-----+ | |
    >>>> | | | | |
    >>>> | +-----+ | |
    >>>> | | | |
    >>>> +-------------------+ Vin [R2] |
    >>>> | | | | | |
    >>>> | D /-|--+ | [RL]
    >>>> |K G---< | | |
    >>>> [REF] S \+|-------+-----+ |
    >>>> | | | | | |
    >>>> | | | [R3] [C1] |
    >>>> | | | | | |
    >>>> GND>----+-----------+-------+--------+-----+-->>--+
    >>>>
    >>>>
    >>>> Use a little high-voltage FET to drive the big FET's gate. They're
    >>>> cheap and it doesn't take much (damn near nothing) to drive them. Use
    >>>> a micropower opamp and you can get its supply voltage from a resistor
    >>>> and a low-current shunt reference tied to the 400V rail (or even just
    >>>> a resistive divider) The Zener is to make sure the big MOSFET's gate
    >>>> voltage never goes higher than it's supposed to, WRT to the source,
    >>>> R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    >>>> oscillating.
    >>>
    >>>It cannot oscillate no matter what value you use for C1.
    >>>Study it carefully and I'm sure you can see why.

    >>
    >> ---
    >> Typical behavior for you. As the erroree, when you find what you
    >> think is an error, instead of simply stating what you think it is that
    >> makes it an error, you hold back and try to get some mileage out of it
    >> by requiring a lot of work to be done by whom you consider to be the
    >> errorer.

    >
    >The post you quoted is one I canceled a couple of
    >minutes after hitting send. I mistakenly read your
    >upper MOSFET as a reversed P-channel device,
    >assuming, incorrectly, that you intended to produce
    >the 400V output first mentioned by the OP. As I
    >was reading your schematic, filling in the missing
    >polarity, it looked like a bistable latch. And if that
    >was what you had drawn, (or meant to draw), it
    >would have taken little time to spot it.
    >
    >> In this case, good catch, but... the larger C1 becomes, the greater
    >> the output ripple becomes, until it starts to look like an
    >> oscillation. The best C1 is no C1, according to bitethedust.asc which
    >> you can find on abse and which you can run if you've downloaded
    >> LTSPICE

    >
    >I'm game. It's not showing up on my newserver
    >in alt.binaries.schematics.electronic . Can you
    >either email it or state what part values and
    >transistors you used? Or post, the .asc, which
    >is ASCII, so can be pasted into a post.


    ---
    I can, but I won't. You know where it is, so find it and fend for
    yourself. Or piss off.
    ---

    >I presume your comments apply to my post of
    >12:50, where I asked about loop gain shifts
    >and dominant poles. Since you elect to not
    >answer that, I want to simulate your circuit
    >and see for myself.


    ---
    Fine. You know where the file is, so retrieve it and have at it.
    ---

    >Where did the output ripple come from? I can
    >see no source for it in your schematic other
    >than an oscillation. I'm about 95% confidant
    >that it will oscillate until C1 becomes huge.
    >The only question is where the limiting occurs.


    ---
    Geez, I thought you said in an earlier post that there was _no way_
    the circuit could oscillate, regardless of the value of C1.

    Backpedaling, you phony piece of shit?

    --
    John Fields
     
    John Fields, Mar 23, 2005
    #11
  12. Larry Brasfield

    John Fields Guest

    On Wed, 23 Mar 2005 00:18:43 GMT, "Genome" <>
    wrote:


    >John, that is piss poor. Whilst Larry might not have the bananas to
    >tell you why he will probably sweat buckets coming up with some
    >'reasons'. You have done yourself and Spice a big unfavour.


    ---
    I'm sorry to hear that and, since I respect your opinion, I'd like to
    hear where I've gone awry.

    --
    John Fields
     
    John Fields, Mar 23, 2005
    #12
  13. Larry Brasfield

    Genome Guest

    "John Fields" <> wrote in message
    news:...
    > On Wed, 23 Mar 2005 00:18:43 GMT, "Genome" <>
    > wrote:
    >
    >
    > >John, that is piss poor. Whilst Larry might not have the bananas to
    > >tell you why he will probably sweat buckets coming up with some
    > >'reasons'. You have done yourself and Spice a big unfavour.

    >
    > ---
    > I'm sorry to hear that and, since I respect your opinion, I'd like

    to
    > hear where I've gone awry.
    >
    > --
    > John Fields


    OK, not that I'll nail it but....

    You drive your control mosfet through a resistor from your error
    amplifier. That resistor forms a pole with the mosfets input
    capacitance.

    The drain of your control mosfet drives the pass mosfet. The control
    mosfet acts as a current sink. Your pass mosfet has its gate
    capacitance. That gives you another pole, current driving a capacitor.

    At some point your system goes second order and will therefore be
    unstable.

    You add your compensating capacitor at the input to your error
    amplifier and you drive it third order and things get worse.

    Your op-amp model includes the line

    Avol=1Meg GBW=10Meg Slew=10Meg

    It's a first order model in itself, those poles are adding up. Then
    you don't add a local loop around that op-amp and run it balls to the
    wall.

    If you probe the output of the op-amp in your spice model then you
    will see that it's bouncing up and down.

    OK, that's not exhaustive and I've not suggested any solutions but,
    there you go.

    Oh, and a pre-emptive...... **** off Larry.

    I'm off to bed.


    DNA
     
    Genome, Mar 23, 2005
    #13
  14. Demonstrating a reading comphrension problem here.
    Reversable Derf transform applied.

    "John Fields" <> wrote in message
    news:...
    > On Tue, 22 Mar 2005 15:57:07 -0800, "Larry Brasfield"
    > <> wrote:
    >>"John Fields" <> wrote in message
    >> news:...
    >>> On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    >>> <> wrote:

    ....
    >>>>It cannot oscillate no matter what value you use for C1.
    >>>>Study it carefully and I'm sure you can see why.

    ....
    >>The post you quoted is one I canceled a couple of
    >>minutes after hitting send. I mistakenly read your
    >>upper MOSFET as a reversed P-channel device,
    >>assuming, incorrectly, that you intended to produce
    >>the 400V output first mentioned by the OP. As I
    >>was reading your schematic, filling in the missing
    >>polarity, it looked like a bistable latch.

    ....
    >I presume your comments apply to my post of
    >12:50, where I asked about loop gain shifts
    >and dominant poles.

    ....
    >>Where did the output ripple come from? I can
    >>see no source for it in your schematic other
    >>than an oscillation. I'm about 95% confidant
    >>that it will oscillate until C1 becomes huge.
    >>The only question is where the limiting occurs.

    > ---
    > Geez, I thought you said in an earlier post that there was _no way_
    > the circuit could oscillate, regardless of the value of C1.
    >
    > Backpedaling [d1]?


    Let's review the sequence of events here:
    0. JF posts a schematic.
    1. LB posts "cannot oscillate ... Study it carefully".
    2. LB spots an error in said post and cancels it.
    3. LB posts, 13 minutes after 1, about loop gain and dominant poles.
    4. JF replies to something by quoting the cancelled post, 2 hours
    and 32 minutes after post 3, (the correction) was posted.
    5. LB replies, informing JF that post 1 cancelled, post 3 is up,
    and claiming confidence that JF designed an oscillator.
    6. JF replies, 1 hour and 13 minutes later, noting that posts 1 and 5
    are inconsistent, suggests post 5 should be called "backpedaling".

    To me, that sequence of events clearly indicates, at best, a
    severe reading comprehension problem. Either that, or in
    JFWorld, an error caught and fixed by the same person,
    without any outside impetus, and freely acknowledged,
    is to be deemed "backpedaling". The problem with that
    view is that the "retreat" was already history, long before
    you came up with any reply to either the canceled post
    or its replacement. You've got the tense wrong.

    I find it odd that you are happy to castigate me for never
    voluntarily changing my mind, and then, given an instance
    of that very action, latch onto it as cause for denigration.
    I hope you will forgive me for not caring what you think.

    --
    --Larry Brasfield
    email:
    Above views may belong only to me.

    Derf transform extractions follow:
    Dreck:
    [d1: , you phony piece of shit]
     
    Larry Brasfield, Mar 23, 2005
    #14
  15. Larry Brasfield

    Fred Bloggs Guest

    Larry Brasfield wrote:
    > "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    > news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...
    >
    >>"Larry Brasfield" <> wrote in news:%
    >>TY%d.35$e%:

    >
    > ...
    > Regarding circuit shown at:
    > https://netfiles.uiuc.edu/mnoone/www/Linearamplifierwithfet.jpg
    > [Why the FET dies resolved.]
    >
    >
    >>OK then well now I'm just confused - how would you switch a very high
    >>voltage signal with a mosfet with a low voltage input?

    >
    >
    > To do that in a DC coupled manner with a ground
    > referenced load and a ground referenced controller
    > normally requires at least 1 more transistor, itself
    > having similar HV withstand. The process of getting
    > a signal from one voltage range to another is often
    > called "translating". A common base amplifier could
    > do it for your application.


    Oh yeah? But that does not answer how you would do it using a MOSFET.
    MOSFETs don't have "base" leads. And a "switch" is entirely different
    from a level translator- you don't know what you're doing, so you're now
    adding additional and inapplicable information to dodge answering the
    simple OP and his simple question.

    >
    > And don't call it "switch" when you mean to drive
    > the FET so that it has varying transconductance.


    "Varying transconductance"? Is that what you mean by linearly? You may
    have the OP impressed with your idiot vocabulary- but the rest of us see
    you for what you are...

    >
    >
    >>I thought one of the
    >>big ideas of fets was that you could take a small input voltage and switch
    >>a large input voltage - but that seems to not be right?

    >
    >
    > That has not been contravened here.


    "Contravened"? What a total pseudo-intellectual misuse and
    misapplication of a simple word...you mean /you/ can't tell him anything
    to make a determination one or the other- not quite the same as
    "contravene".

    >
    >
    >>Thanks,

    >
    >
    > You're welcome. I've set followups to sci.electronics.basics
    > because this kind of discussion is more topical there.
    >


    You mean you're trying to pull out of said where your bullsh_t will be
    scrutinized. Run and hide, Mary.
     
    Fred Bloggs, Mar 23, 2005
    #15
  16. Larry Brasfield

    Fred Bloggs Guest

    Larry Brasfield wrote:
    > "Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    > news:Xns96217F7D8C823mnooneuiucedu127001@216.196.97.136...
    >
    >>"Larry Brasfield" <> wrote in
    >>news:YiZ%d.45$e%:
    >>
    >>>"Michael Noone" <mnoone.uiuc.edu@127.0.0.1> wrote in message
    >>> news:Xns96217A2E8B647mnooneuiucedu127001@216.196.97.136...

    >>

    > ...
    >
    >>>>OK then well now I'm just confused - how would you switch a very high
    >>>>voltage signal with a mosfet with a low voltage input?
    >>>
    >>>To do that in a DC coupled manner with a ground
    >>>referenced load and a ground referenced controller
    >>>normally requires at least 1 more transistor, itself
    >>>having similar HV withstand. The process of getting
    >>>a signal from one voltage range to another is often
    >>>called "translating". A common base amplifier could
    >>>do it for your application.

    >>
    >>Could you reccomend a transistor that would be able to serve this
    >>function? I've looked before for high voltage transistors and found very
    >>little.

    >
    >
    > Go to www.onsemi.com and try again.


    Don't know of any HV transistors off the top of your head? Hey, if
    you're as clueless as the OP then why are you posing as the big expert
    answering his questions?

    >
    >
    >>>And don't call it "switch" when you mean to drive
    >>>the FET so that it has varying transconductance.

    >>
    >>Well - actually I meant switch. Switching is the usage of mosfets that
    >>I'm familiar with, using them to make a linear output is something I'm
    >>not fully comfortable with just yet. I was asking in general, not about
    >>the schematic that I posted.

    >
    >
    > In the context you used the word, it was inappropriate
    > and indicates, to people sharing the same language,
    > that you either misconceive the circuit or are not yet
    > familiar with what the word really means.


    That's the typical pseudo-intellectual dodge: if you're clueless about
    technical issues, introduce peripheral material about semantics. The OP
    may be too damned dumb to know a fake when he reads one, but not the ret
    of us.

    >
    > ...
    >
    >>So - once a high volage transistor is used to drive the gate, what else
    >>do I need to change to make the circuit work?

    >
    >
    > I would use this configuration:
    >
    > VCC
    > +
    > .----)---.
    > | |
    > .-. .-.
    > | | | |
    > | | | |
    > '-' '-'
    > | |
    > | |
    > o-----||-+
    > | ||->
    > | ||-+
    > | |
    > | |
    > | o------.OUT
    > | | |
    > || | | .-.
    > .-----||--. |/ | | |
    > | || | GND-| | | |
    > | | |> | '-'
    > ___ | |\| | | | |
    > GND-|___|-o--|-\ | ___ | | GND
    > | >---o---|___|----o |
    > .--|+/ . |
    > | |/| | |
    > | GND-|<- |
    > | |
    > ___ | ___ |
    > IN -|___|-o---------|___|-----------------'
    > (created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)
    >
    > You can set the resistors associated with the FET to
    > control loop gain while setting the emitter resistor
    > to limit the max gate drive.



    > The response will tend
    > to be stable if you do not set the power amp stage
    > gain too high and make the integrator feedback
    > network pole in about the same place that the
    > power amp stage has its lowest frequency pole.


    Really? And since when the hell does anyone design around "tend to be
    stable" pseudo-intellectual? How does one go about finding the power amp
    stage pole? And placing "network pole" coincident with power amp lowest
    frequency pole?- You mean the "network" zero don't you, mental midget?

    > It inverts, so if your heart is set on the transfer
    > function you posted, you'll need to adjust.


    You're not kidding he needs to make adjustments to things like adding a
    +400V supply and a trash circuit that goes open loop for IN>0. Yeah-
    that's real useful.

    >
    > I still think you need to
    >


    Needs to what? Lost your thoughts? You regurgitated your p.o.s. circuit
    with a bunch of nebulous references to poles and gain control resistors,
    but not a single specific bit of information about any of it. Talk about
    "garbage electronics"- take at look at your worthless posts.
     
    Fred Bloggs, Mar 23, 2005
    #16
  17. Larry Brasfield

    Fred Bloggs Guest

    Michael Noone wrote:
    > "Larry Brasfield" <> wrote in
    > news:8D_%d.51$e%:
    >
    >
    >>Go to www.onsemi.com and try again.

    >
    >
    > OK - well I'm not entirely sure what I should be looking for, so I just
    > looked for a high voltage NPN BJT, and found this:
    > http://www.onsemi.com/pub/Collateral/MPSA44-D.PDF - Is that what you
    > were describing?
    >
    >
    >
    >>>So - once a high volage transistor is used to drive the gate, what

    >>

    > else
    >
    >>>do I need to change to make the circuit work?

    >>
    >>I would use this configuration:
    >>
    >> VCC
    >> +
    >> .----)---.
    >> | |
    >> .-. .-.
    >> | | | |
    >> | | | |
    >> '-' '-'
    >> | |
    >> | |
    >> o-----||-+
    >> | ||->
    >> | ||-+
    >> | |
    >> | |
    >> | o------.OUT
    >> | | |
    >> || | | .-.
    >> .-----||--. |/ | | |
    >> | || | GND-| | | |
    >> | | |> | '-'
    >> ___ | |\| | | | |
    >> GND-|___|-o--|-\ | ___ | | GND
    >> | >---o---|___|----o |
    >> .--|+/ . |
    >> | |/| | |
    >> | GND-|<- |
    >> | |
    >> ___ | ___ |
    >> IN -|___|-o---------|___|-----------------'
    >>(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)
    >>
    >>You can set the resistors associated with the FET to
    >>control loop gain while setting the emitter resistor
    >>to limit the max gate drive. The response will tend
    >>to be stable if you do not set the power amp stage
    >>gain too high and make the integrator feedback
    >>network pole in about the same place that the
    >>power amp stage has its lowest frequency pole.
    >>It inverts, so if your heart is set on the transfer
    >>function you posted, you'll need to adjust.
    >>
    >>I still think you need to

    >
    >
    > Correct me if I'm completely wrong [I probabaly am :)] - but to me it
    > looks like The input could get stuck sinking a decent amount of current.
    > The input to this circuit is coming from a very low current (I think
    > about 2ma max or so) DAC board, so that needs to be avoided. I guess I'd
    > just buffer the input if that is the case - but I thought I should ask
    > to be sure.
    >
    > Also - I'm having alot of difficulty figuring out what exactly is
    > happening in this circuit. To me - it looks like the output from the op-
    > amp just goes through a resistor and is then grounded. It's as if the
    > output form the op-amp pretty much doesn't do anything at all.
    > Similarly, it looks like both the base and the emitter of the transistor
    > are grounded, which again seems odd. Maybe I'm misunderstanding the
    > circuit? To me it looks like the node connecting the resistor on the
    > output of the op-amp and the emitter of the bjt is grounded, but maybe
    > I'm wrong?
    >
    > Thanks for all your help, and for putting up with all my questions :)
    >
    > -Michael


    LOL! GOOD CALL! And no response from the fake, Larry Brasfield. Larry
    Brasfield gets put down by a complete newbie- Larry Brasfield gets
    exposed as a fake, and Larry Brasfield ***skulks*** off- nowhere to be
    found. LOL!!!!!!!!!!!!!
     
    Fred Bloggs, Mar 23, 2005
    #17
  18. Larry Brasfield

    Fred Bloggs Guest

    Larry Brasfield wrote:
    > "John Fields" <> wrote in message
    > news:...
    >
    >>On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    >><mnoone.uiuc.edu@127.0.0.1> wrote:

    >
    > ...
    >
    >>+400V>--+-----+---D S---+----------+-------->>--+
    >> | | G | | |
    >> | | | [ZENER] | |
    >> [R1] [R2] | |K | |
    >> | | +-----+ | |
    >> | | | | |
    >> | +-----+ | |
    >> | | | |
    >> +-------------------+ Vin [R2] |
    >> | | | | | |
    >> | D /-|--+ | [RL]
    >> |K G---< | | |
    >> [REF] S \+|-------+-----+ |
    >> | | | | | |
    >> | | | [R3] [C1] |
    >> | | | | | |
    >>GND>----+-----------+-------+--------+-----+-->>--+
    >>
    >>
    >>Use a little high-voltage FET to drive the big FET's gate. They're
    >>cheap and it doesn't take much (damn near nothing) to drive them. Use
    >>a micropower opamp and you can get its supply voltage from a resistor
    >>and a low-current shunt reference tied to the 400V rail (or even just
    >>a resistive divider) The Zener is to make sure the big MOSFET's gate
    >>voltage never goes higher than it's supposed to, WRT to the source,
    >>R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    >>oscillating.

    >
    >
    > It cannot oscillate no matter what value you use for C1.
    > Study it carefully and I'm sure you can see why.
    >


    Okay- let's see- your own circuit is a blatant p.o.s., the OP called you
    on it, you ran away from answering, and now you come over to make a
    comment on JF's circuit? A dumb comment by the way- two high gain stages
    in the loop and you say it can't oscillate- pathetic.
     
    Fred Bloggs, Mar 23, 2005
    #18
  19. Larry Brasfield

    Fred Bloggs Guest

    Larry Brasfield wrote:
    > "John Fields" <> wrote in message
    > news:...
    >
    >>On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    >><> wrote:
    >>
    >>
    >>>"John Fields" <> wrote in message
    >>>news:...
    >>>
    >>>>On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
    >>>><mnoone.uiuc.edu@127.0.0.1> wrote:
    >>>
    >>>...
    >>>
    >>>>+400V>--+-----+---D S---+----------+-------->>--+
    >>>> | | G | | |
    >>>> | | | [ZENER] | |
    >>>> [R1] [R2] | |K | |
    >>>> | | +-----+ | |
    >>>> | | | | |
    >>>> | +-----+ | |
    >>>> | | | |
    >>>> +-------------------+ Vin [R2] |
    >>>> | | | | | |
    >>>> | D /-|--+ | [RL]
    >>>> |K G---< | | |
    >>>> [REF] S \+|-------+-----+ |
    >>>> | | | | | |
    >>>> | | | [R3] [C1] |
    >>>> | | | | | |
    >>>>GND>----+-----------+-------+--------+-----+-->>--+
    >>>>
    >>>>
    >>>>Use a little high-voltage FET to drive the big FET's gate. They're
    >>>>cheap and it doesn't take much (damn near nothing) to drive them. Use
    >>>>a micropower opamp and you can get its supply voltage from a resistor
    >>>>and a low-current shunt reference tied to the 400V rail (or even just
    >>>>a resistive divider) The Zener is to make sure the big MOSFET's gate
    >>>>voltage never goes higher than it's supposed to, WRT to the source,
    >>>>R2 R3 is the 40:1 divider, and C1 is to keep the thing from
    >>>>oscillating.
    >>>
    >>>It cannot oscillate no matter what value you use for C1.
    >>>Study it carefully and I'm sure you can see why.

    >>
    >>---
    >>Typical behavior for you. As the erroree, when you find what you
    >>think is an error, instead of simply stating what you think it is that
    >>makes it an error, you hold back and try to get some mileage out of it
    >>by requiring a lot of work to be done by whom you consider to be the
    >>errorer.

    >
    >
    > The post you quoted is one I canceled a couple of
    > minutes after hitting send. I mistakenly read your
    > upper MOSFET as a reversed P-channel device,
    > assuming, incorrectly, that you intended to produce
    > the 400V output first mentioned by the OP. As I
    > was reading your schematic, filling in the missing
    > polarity, it looked like a bistable latch. And if that
    > was what you had drawn, (or meant to draw), it
    > would have taken little time to spot it.


    Bistable latch? More big technical words from the clueless lightweight
    and poser? Looks like a common drain buffering his common source stage
    to me, and anyone else who knows anything at all....

    >
    >
    >>In this case, good catch, but... the larger C1 becomes, the greater
    >>the output ripple becomes, until it starts to look like an
    >>oscillation. The best C1 is no C1, according to bitethedust.asc which
    >>you can find on abse and which you can run if you've downloaded
    >>LTSPICE

    >
    >
    > I'm game. It's not showing up on my newserver
    > in alt.binaries.schematics.electronic . Can you
    > either email it or state what part values and
    > transistors you used? Or post, the .asc, which
    > is ASCII, so can be pasted into a post.
    >
    > I presume your comments apply to my post of
    > 12:50, where I asked about loop gain shifts
    > and dominant poles. Since you elect to not
    > answer that, I want to simulate your circuit
    > and see for myself.


    Why should he answer your questions? You don't answer any questions put
    to you.....Sounds like a free-loader looking for a free education to me.

    >
    > Where did the output ripple come from? I can
    > see no source for it in your schematic other
    > than an oscillation. I'm about 95% confidant
    > that it will oscillate until C1 becomes huge.
    > The only question is where the limiting occurs.


    "confidant"? This underlying implicit assumption you make about people
    valuing your opinion is the height of mental illness- especially after
    all the demonstration that you don't know your ass from a hole in the
    ground.
     
    Fred Bloggs, Mar 23, 2005
    #19
  20. Larry Brasfield

    Fred Bloggs Guest

    Larry Brasfield wrote:
    > Demonstrating a reading comphrension problem here.
    > Reversable Derf transform applied.
    >
    > "John Fields" <> wrote in message
    > news:...
    >
    >>On Tue, 22 Mar 2005 15:57:07 -0800, "Larry Brasfield"
    >><> wrote:
    >>
    >>>"John Fields" <> wrote in message
    >>>news:...
    >>>
    >>>>On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
    >>>><> wrote:
    >>>

    > ...
    >
    >>>>>It cannot oscillate no matter what value you use for C1.
    >>>>>Study it carefully and I'm sure you can see why.
    >>>>

    > ...
    >
    >>>The post you quoted is one I canceled a couple of
    >>>minutes after hitting send. I mistakenly read your
    >>>upper MOSFET as a reversed P-channel device,
    >>>assuming, incorrectly, that you intended to produce
    >>>the 400V output first mentioned by the OP. As I
    >>>was reading your schematic, filling in the missing
    >>>polarity, it looked like a bistable latch.

    >>

    > ...
    >
    >>I presume your comments apply to my post of
    >>12:50, where I asked about loop gain shifts
    >>and dominant poles.

    >
    > ...
    >
    >>>Where did the output ripple come from? I can
    >>>see no source for it in your schematic other
    >>>than an oscillation. I'm about 95% confidant
    >>>that it will oscillate until C1 becomes huge.
    >>>The only question is where the limiting occurs.

    >>
    >>---
    >>Geez, I thought you said in an earlier post that there was _no way_
    >>the circuit could oscillate, regardless of the value of C1.
    >>
    >>Backpedaling [d1]?

    >
    >
    > Let's review the sequence of events here:
    > 0. JF posts a schematic.
    > 1. LB posts "cannot oscillate ... Study it carefully".
    > 2. LB spots an error in said post and cancels it.
    > 3. LB posts, 13 minutes after 1, about loop gain and dominant poles.
    > 4. JF replies to something by quoting the cancelled post, 2 hours
    > and 32 minutes after post 3, (the correction) was posted.
    > 5. LB replies, informing JF that post 1 cancelled, post 3 is up,
    > and claiming confidence that JF designed an oscillator.
    > 6. JF replies, 1 hour and 13 minutes later, noting that posts 1 and 5
    > are inconsistent, suggests post 5 should be called "backpedaling".
    >
    > To me, that sequence of events clearly indicates, at best, a
    > severe reading comprehension problem. Either that, or in
    > JFWorld, an error caught and fixed by the same person,
    > without any outside impetus, and freely acknowledged,
    > is to be deemed "backpedaling". The problem with that
    > view is that the "retreat" was already history, long before
    > you came up with any reply to either the canceled post
    > or its replacement. You've got the tense wrong.
    >
    > I find it odd that you are happy to castigate me for never
    > voluntarily changing my mind, and then, given an instance
    > of that very action, latch onto it as cause for denigration.
    > I hope you will forgive me for not caring what you think.
    >


    Nah- the sequence of events: LB can't understand anything, LB looking
    for a way to evade OP's questions about his own dumbass p.o.s. circuit,
    LB now trying to create smoke screen to look busy.
    Yep- LB is quite the blatant fake, phony, pseudo-intellectual p.o.s.
     
    Fred Bloggs, Mar 23, 2005
    #20
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