"John Fields" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed)...
> On Tue, 22 Mar 2005 12:37:39 -0800, "Larry Brasfield"
> <(E-Mail Removed)> wrote:
>
>>"John Fields" <(E-Mail Removed)> wrote in message
>> news:(E-Mail Removed)...
>>> On Tue, 22 Mar 2005 12:32:16 -0600, Michael Noone
>>> <mnoone.uiuc.edu@127.0.0.1> wrote:
>>...
>>> +400V>--+-----+---D S---+----------+-------->>--+
>>> | | G | | |
>>> | | | [ZENER] | |
>>> [R1] [R2] | |K | |
>>> | | +-----+ | |
>>> | | | | |
>>> | +-----+ | |
>>> | | | |
>>> +-------------------+ Vin [R2] |
>>> | | | | | |
>>> | D /-|--+ | [RL]
>>> |K G---< | | |
>>> [REF] S \+|-------+-----+ |
>>> | | | | | |
>>> | | | [R3] [C1] |
>>> | | | | | |
>>> GND>----+-----------+-------+--------+-----+-->>--+
>>>
>>>
>>> Use a little high-voltage FET to drive the big FET's gate. They're
>>> cheap and it doesn't take much (damn near nothing) to drive them. Use
>>> a micropower opamp and you can get its supply voltage from a resistor
>>> and a low-current shunt reference tied to the 400V rail (or even just
>>> a resistive divider) The Zener is to make sure the big MOSFET's gate
>>> voltage never goes higher than it's supposed to, WRT to the source,
>>> R2 R3 is the 40:1 divider, and C1 is to keep the thing from
>>> oscillating.
>>
>>It cannot oscillate no matter what value you use for C1.
>>Study it carefully and I'm sure you can see why.
>
> ---
> Typical behavior for you. As the erroree, when you find what you
> think is an error, instead of simply stating what you think it is that
> makes it an error, you hold back and try to get some mileage out of it
> by requiring a lot of work to be done by whom you consider to be the
> errorer.
The post you quoted is one I canceled a couple of
minutes after hitting send. I mistakenly read your
upper MOSFET as a reversed P-channel device,
assuming, incorrectly, that you intended to produce
the 400V output first mentioned by the OP. As I
was reading your schematic, filling in the missing
polarity, it looked like a bistable latch. And if that
was what you had drawn, (or meant to draw), it
would have taken little time to spot it.
> In this case, good catch, but... the larger C1 becomes, the greater
> the output ripple becomes, until it starts to look like an
> oscillation. The best C1 is no C1, according to bitethedust.asc which
> you can find on abse and which you can run if you've downloaded
> LTSPICE
I'm game. It's not showing up on my newserver
in alt.binaries.schematics.electronic . Can you
either email it or state what part values and
transistors you used? Or post, the .asc, which
is ASCII, so can be pasted into a post.
I presume your comments apply to my post of
12:50, where I asked about loop gain shifts
and dominant poles. Since you elect to not
answer that, I want to simulate your circuit
and see for myself.
Where did the output ripple come from? I can
see no source for it in your schematic other
than an oscillation. I'm about 95% confidant
that it will oscillate until C1 becomes huge.
The only question is where the limiting occurs.
--
--Larry Brasfield
email:
(E-Mail Removed)
Above views may belong only to me.