PCB Power Trace Widths, Ground Planes, and Routing

Hello,

** I feel somewhat overwhelmed by my pcb design task, so I appologize
in advance for the length/convoluted-ness of this post. I have
attempted to compact and clarify as best as I can.

I am designing a PCB of an embedded system with mostly SMT parts. The
board includes audio (TI TLV320AIC1106) and ethernet subsections
(Cirrus Logic CS8900A). It also includes an Oki Semiconductor ML67Q5003
ARM microprocessor running at 20MHz (4x PLL) clocked by a 5MHz
oscillator. It draws not more than 0.5A, is only two layers, and has
three regulated voltages (5, 3.3, 2.5)from a 16V 500mA wall-wart
transformer.

Using a trace width calculator at www.33each.com, I find that the 8mil
signal traces on my board are wide enough to route power. Should I make
them thicker (100mil?) anyway? Thicker traces confuse the Altium Situs
auto-router around my SMT components so I would prefer not to unless
needed.

How important are ground/power planes here? Since this is a two layer
board with close to 500 connections on the pcb, even with a 6x8" board,
space is tight around the SMT chips, so I would like to avoid planes if
possible. If I do add a plane, should I include dead/unconnected copper
portions of the plane? Should planes be placed before or after
auto-routing?

What other considerations should I take? What can make routing easier?
I've been playing with Protel DXP for a few days and was finally able
to generate a fully routed board that I think meets manufacturing
specs, but it was a long iterative process getting here.

Does Advanced Circuits (www.33each.com) have standard hole sizes? Is it
safe to exactly meet there minimum requirements for trace/via/pad
separation on much of the board?

Answers or feedback to any of these questions are much appreciated.
Happy Holidays,
Chris

On 25 Dec 2004 05:20:55 -0800, "Apparatus" <(E-Mail Removed)>
wrote:

>Hello,
>
>** I feel somewhat overwhelmed by my pcb design task, so I appologize
>in advance for the length/convoluted-ness of this post. I have
>attempted to compact and clarify as best as I can.
>
>I am designing a PCB of an embedded system with mostly SMT parts. The
>board includes audio (TI TLV320AIC1106) and ethernet subsections
>(Cirrus Logic CS8900A). It also includes an Oki Semiconductor ML67Q5003
>ARM microprocessor running at 20MHz (4x PLL) clocked by a 5MHz
>oscillator. It draws not more than 0.5A, is only two layers, and has
>three regulated voltages (5, 3.3, 2.5)from a 16V 500mA wall-wart
>transformer.
>
>Using a trace width calculator at www.33each.com, I find that the 8mil
>signal traces on my board are wide enough to route power. Should I make
>them thicker (100mil?) anyway? Thicker traces confuse the Altium Situs
>auto-router around my SMT components so I would prefer not to unless
>needed.
>
>How important are ground/power planes here? Since this is a two layer
>board with close to 500 connections on the pcb, even with a 6x8" board,
>space is tight around the SMT chips, so I would like to avoid planes if
>possible. If I do add a plane, should I include dead/unconnected copper
>portions of the plane? Should planes be placed before or after
>auto-routing?
>
>What other considerations should I take? What can make routing easier?
>I've been playing with Protel DXP for a few days and was finally able
>to generate a fully routed board that I think meets manufacturing
>specs, but it was a long iterative process getting here.
>
>Does Advanced Circuits (www.33each.com) have standard hole sizes? Is it
>safe to exactly meet there minimum requirements for trace/via/pad
>separation on much of the board?
>
>Answers or feedback to any of these questions are much appreciated.
>Happy Holidays,
>Chris

If it's only 2 layers and has no ground plane, and power and ground
are just skinny routed traces, I'd be astonished if it actually
worked.

8 mils is scairy for power, terrifying for ground. It can certainly
handle the current (in the sense of not getting too hot) but the
resistance and inductance can make big trouble.

The most critical thing will be ground. Is this just a bunch of
autorouted 8-mil traces? That will be bad news.

If you have a lot of area to kill and insist on a 2-layer board,
manually create a ground grid of fat (100 mil, maybe) traces using
both sides, plop a via at each intersection, glue all that down, and
route around it with signals.

Better yet, go to 4 layers: solid ground l3, regional power pours on
l2, traces on l1 and l4, with some more routing on l2 around the pours
maybe.

John

On Sat, 25 Dec 2004 05:20:55 -0800, Apparatus wrote:

> Hello,
>
> ** I feel somewhat overwhelmed by my pcb design task, so I appologize
> in advance for the length/convoluted-ness of this post. I have
> attempted to compact and clarify as best as I can.
>
> I am designing a PCB of an embedded system with mostly SMT parts. The
> board includes audio (TI TLV320AIC1106) and ethernet subsections
> (Cirrus Logic CS8900A). It also includes an Oki Semiconductor ML67Q5003
> ARM microprocessor running at 20MHz (4x PLL) clocked by a 5MHz
> oscillator. It draws not more than 0.5A, is only two layers, and has
> three regulated voltages (5, 3.3, 2.5)from a 16V 500mA wall-wart
> transformer.
>
> Using a trace width calculator at www.33each.com, I find that the 8mil
> signal traces on my board are wide enough to route power. Should I make
> them thicker (100mil?) anyway? Thicker traces confuse the Altium Situs
> auto-router around my SMT components so I would prefer not to unless
> needed.
>
> How important are ground/power planes here? Since this is a two layer
> board with close to 500 connections on the pcb, even with a 6x8" board,
> space is tight around the SMT chips, so I would like to avoid planes if
> possible. If I do add a plane, should I include dead/unconnected copper
> portions of the plane? Should planes be placed before or after
> auto-routing?
>
> What other considerations should I take? What can make routing easier?
> I've been playing with Protel DXP for a few days and was finally able
> to generate a fully routed board that I think meets manufacturing
> specs, but it was a long iterative process getting here.
>
> Does Advanced Circuits (www.33each.com) have standard hole sizes? Is it
> safe to exactly meet there minimum requirements for trace/via/pad
> separation on much of the board?
>
> Answers or feedback to any of these questions are much appreciated.
> Happy Holidays,
> Chris

I wouldn't attempt to do what you are doing without at least 4 layers.
This will make routing a lot easier, too, because power (or at least
ground) is basically done.

As for power traces of 0.008", AFAIK, that is totally unworkable, although
I have never tried it. The problem is that 8 mil traces have a lot of
inductance, and digital chips draw current in spikes. So it is hard to
ensure that there is enough current available when it is needed. Also, you
can no longer be sure that at any given moment, all the chip grounds are
at the same potential. This could cause huge problems.

I think I would go with 4 layers and put in a GND plane, and one positive
power plane. Whichever of your 3 voltages is most common I would make into
a power plane. Personally, I would not route any traces on this power
plane. I might put in some islands of different voltages, but according to
my training, there are precautions that must be followed when you do this.
For example, when you route a high-speed signal on an outer layer, it is
referenced to the underlying plane. If the signal crosses a split in
the plane, you have to decouple directly across the plane split with a
high-frequency capacitor, and the capacitor has to be near the signal.
This is a change of reference.

If most of your signals are not high speed, then you may get away with not
worrying about this. But at least you should do it for the clocks and
any highly active buses.

Sounds like you may be in slightly over your head, but hey, that's how we
learn. ;-)

I hope you allow enough time in the schedule to do the board layout twice.
Especially if it requires FCC testing.

HTH

--Mac

Thank you for your informative replies.

I'm using a two layer board since it is $33 at www.33each.com with the
student discount. I suppose I could go to a four layer board. How much
more do these usually run? (The price isn't listed on 33each.com. I
need to call for a quote.)

What speed qualifies as high speed? Which buses qualify as highly
active buses? The ARM is able to be clocked up to 66MHz, but I'm
running it at 20MHz (4x 5MHz osc. via PLL) to avoid much these high
speed effects. The ethernet section is running at 20MHz as well, but
off a separate crystal to allow me to clock the ARM faster,
independently of the CS8900. The TI Codec is running at 2.048MHz of
another osc. The ARM has an 18-bits of the address bus running to SRAM,
1-bit to the LCD controller, and 3-bits to the CS8900. The 16-bit data
bus runs 16-bits to SRAM and the CS8900, and 8-bits to the TI Codec and
LCD Controller. During development, SRAM will hold program code and be
frequently accessed. The TI Codec and CS8900 will be the other two
frequently accessed chips (VoIP application).

Should I make separate analog ground planes for the TI Codec and
CS8900? Why do the chips have separate analog and digital grounds (AVss
and DVss)? Can I connect these to one ground plane? If to separate
ground planes, how should the planes connect to ground.

The 5V is to power an onboard LCD the CPLD LCD controller. The 2.5V is
the supply for the ARM core. The rest of the system is 3.3V. So I
should make the power plane 3.3V and run 100 mil traces in the same
layer (maybe around the edges?) for the other two supplies? How can I
tell the auto-router to make the trace smaller as it gets closer to the
SMT chips? Currently the auto-router tries to run 100mil traces
straight to the SMT pins and looks like it shorts them, though that
could simply be a visual effect. I'm using Protel DXP.

Since this is a student project, I don't need to meet FCC testing. If
you're interested in the class, here is the website:
http://wolverine.caltech.edu/eecs53/

Cheers,
Chris

On 25 Dec 2004 19:23:09 -0800, "Apparatus" <(E-Mail Removed)>
wrote:

>Thank you for your informative replies.
>
>I'm using a two layer board since it is $33 at www.33each.com with the
>student discount. I suppose I could go to a four layer board. How much
>more do these usually run? (The price isn't listed on 33each.com. I
>need to call for a quote.)
>

Spend a few more bucks on a 4-layer. You want this to work the first
time, don't you?

>What speed qualifies as high speed? Which buses qualify as highly
>active buses? The ARM is able to be clocked up to 66MHz, but I'm
>running it at 20MHz (4x 5MHz osc. via PLL) to avoid much these high
>speed effects. The ethernet section is running at 20MHz as well, but
>off a separate crystal to allow me to clock the ARM faster,
>independently of the CS8900. The TI Codec is running at 2.048MHz of
>another osc. The ARM has an 18-bits of the address bus running to SRAM,
>1-bit to the LCD controller, and 3-bits to the CS8900. The 16-bit data
>bus runs 16-bits to SRAM and the CS8900, and 8-bits to the TI Codec and
>LCD Controller. During development, SRAM will hold program code and be
>frequently accessed. The TI Codec and CS8900 will be the other two
>frequently accessed chips (VoIP application).
>

The frequency isn't as important as the edge rates and power supply
dI/dT. A "fast" part run at a lower-than-max clock rate still needs to
be treated as a fast part.


>Should I make separate analog ground planes for the TI Codec and
>CS8900?

No.

> Why do the chips have separate analog and digital grounds (AVss
>and DVss)?

So that, internal to the chip, digital ground bounce doesn't mess up
the analog stuff too badly.


>Can I connect these to one ground plane?

Yes.

>
>The 5V is to power an onboard LCD the CPLD LCD controller. The 2.5V is
>the supply for the ARM core. The rest of the system is 3.3V. So I
>should make the power plane 3.3V and run 100 mil traces in the same
>layer (maybe around the edges?) for the other two supplies?

I usually make pour pours around each chip at the appropriate
voltages. If things work out, you can slice up the power plane into
cleverly shaped islands that connect everything with fat regions
everywhere. If not, use power islands around chips and run fat power
feeders (50-100 mils) to the islands from your power supplies.



> How can I
>tell the auto-router to make the trace smaller as it gets closer to the
>SMT chips?

99.99% of autorouters suck 99.99% of the time. Just do it by hand.
Routing is fun.

John

On Sat, 25 Dec 2004 19:23:09 -0800, Apparatus wrote:

> Thank you for your informative replies.
>
> I'm using a two layer board since it is $33 at www.33each.com with the
> student discount. I suppose I could go to a four layer board. How much
> more do these usually run? (The price isn't listed on 33each.com. I
> need to call for a quote.)

Check pcbexpress.com, too.

If you don't mind using their free software, you can also use expresspcb.
They are reliable, but a lot of people don't like using them because their
software uses special output formats that aren't compatible with other
vendors.

>
> What speed qualifies as high speed? Which buses qualify as highly
> active buses? The ARM is able to be clocked up to 66MHz, but I'm
> running it at 20MHz (4x 5MHz osc. via PLL) to avoid much these high
> speed effects. The ethernet section is running at 20MHz as well, but
> off a separate crystal to allow me to clock the ARM faster,
> independently of the CS8900. The TI Codec is running at 2.048MHz of
> another osc. The ARM has an 18-bits of the address bus running to SRAM,
> 1-bit to the LCD controller, and 3-bits to the CS8900. The 16-bit data
> bus runs 16-bits to SRAM and the CS8900, and 8-bits to the TI Codec and
> LCD Controller. During development, SRAM will hold program code and be
> frequently accessed. The TI Codec and CS8900 will be the other two
> frequently accessed chips (VoIP application).

All continuous clocks are high speed, no matter how fast they are. Any bus
that runs continuously should be treated as high speed. This includes all
RAM, etc. And, as John Larkin said, the edge rate of the signal can make
it fast, even if the clock rate isn't. I would say all of your buses are
probably high speed. An example of a non-high-speed bus would be the SMBus
serial bus on Intel architecture systems.

Here is a little tip for you. The clocks on digital boards cause 90
percent of signal integrity and RF interference problems. So leave good
clearance around the clock traces (this helps keep them from adding noise
to other signals), and try to avoid changing reference plane when you
route them. That is, if they are next to a ground layer, keep them next to
ground layers. Don't switch to a VCC layer. And if they are next to a VCC
layer, keep them there. This helps keep them from emitting RF. At my
previous job, our standard procedure was to put series resistors near all
clock sources, and shunt capacitors near all clock loads. This allows you
to control the edge rate to keep RF emissions down, and you can slightly
tweak the signal delay if you find you have a skew problem. Often the
resistor would be replaced with a "jumper", and the capacitor would not be
populated. But this is preferable to redesigning the board to incorporate
them if they are needed. Also, avoid routing other signals near the clock
generator, buffer, and multiplier chips. They are infamous for coupling
noise to other signals.

>
> Should I make separate analog ground planes for the TI Codec and CS8900?
> Why do the chips have separate analog and digital grounds (AVss and
> DVss)? Can I connect these to one ground plane? If to separate ground
> planes, how should the planes connect to ground.

Splitting ground planes is problematic because, as I said, you shouldn't
route signals across the split on layers adjacent to the plane, and
usually, you have to. So it is better to stick to one ground plane, and
decouple it appropriately.

I usually filter the AVDD with series inductor and several shunt
capacitors (to ground) of different values and package sizes. I have never
tried not doing this, but I have had good luck so far with this approach.

>
> The 5V is to power an onboard LCD the CPLD LCD controller. The 2.5V is
> the supply for the ARM core. The rest of the system is 3.3V. So I should
> make the power plane 3.3V and run 100 mil traces in the same layer
> (maybe around the edges?) for the other two supplies? How can I tell the
> auto-router to make the trace smaller as it gets closer to the SMT
> chips? Currently the auto-router tries to run 100mil traces straight to
> the SMT pins and looks like it shorts them, though that could simply be
> a visual effect. I'm using Protel DXP.


I've never used an auto-router. Usually other people have manually
routed my boards for me, according to my instructions. Maybe you could
route some of the critical nets manually first, and then submit the job to
the auto-router?

The idea I have in mind for you is to not route traces on the power plane
at all. Instead, I am imagining that you will have a VCC plane that
will mostly be 3.3V, but with an an island of 5 V near the LCD and
CPLD, and island of 2.5 near the ARM (unless it uses both 2.5 and 3.3.
Does it?). Connect the 5V and 2.5V supplies to the islands using wide
traces. I imagine 100 mils would be fine. Be sure to use multiple vias.

If the arm has 3.3V for the I/O supplies, you may find that the 3.3 V and
the 2.5 V are spacially segregated. In BGA's, the innermost area is often
the core voltage with the IO voltages in the outer balls. I don't know if
your ARM chip is like this or not. If it is, try to make an island that
captures all the 2.5V pins or balls, including decoupling caps, but make
it as small as you can, and try to keep it away from 3.3V pins or balls if
you can.


Usually, I don't decide how to cut up the power plane until after I place
most of the parts on the board. Then I set the different voltages to
different colors and try to visualize where the different islands should
go. Sometimes it is hard. Sometimes it is easy. Sometimes you just have to
do the best you can and hope it works. I try to keep the islands
rectangular, or at most slightly pan-handled. It is OK to have multiple
islands of the same voltage, as long as they are connected by fat traces.
Your 100 mils would be plenty, I think. The individual islands should be
decoupled to ground just as if they were continuous planes.

>
> Since this is a student project, I don't need to meet FCC testing.

Good. That makes the job a lot easier.

> If
> you're interested in the class, here is the website:
> http://wolverine.caltech.edu/eecs53/
>
> Cheers,
> Chris

Good luck! Stay on top of it and try to get things done early. This is a
fairly big task if you've never done it before!

--Mac

"Apparatus" <(E-Mail Removed)> wrote:

>Hello,
>
>** I feel somewhat overwhelmed by my pcb design task, so I appologize
>in advance for the length/convoluted-ness of this post. I have
>attempted to compact and clarify as best as I can.
>
>I am designing a PCB of an embedded system with mostly SMT parts. The
>board includes audio (TI TLV320AIC1106) and ethernet subsections
>(Cirrus Logic CS8900A). It also includes an Oki Semiconductor ML67Q5003
>ARM microprocessor running at 20MHz (4x PLL) clocked by a 5MHz
>oscillator. It draws not more than 0.5A, is only two layers, and has
>three regulated voltages (5, 3.3, 2.5)from a 16V 500mA wall-wart
>transformer.

8 mils is too narrow for power. Use at least 16 mils or better 20
mils. If you route the power like a grid and place 100nf bypass
capacitors on the intersection points, you will be fine.

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

"Apparatus" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Thank you for your informative replies.
>
> I'm using a two layer board since it is $33 at www.33each.com with the
> student discount. I suppose I could go to a four layer board. How much
> more do these usually run? (The price isn't listed on 33each.com. I
> need to call for a quote.)
>
> What speed qualifies as high speed? Which buses qualify as highly
> active buses? The ARM is able to be clocked up to 66MHz, but I'm
> running it at 20MHz (4x 5MHz osc. via PLL) to avoid much these high
> speed effects. The ethernet section is running at 20MHz as well, but
> off a separate crystal to allow me to clock the ARM faster,
> independently of the CS8900. The TI Codec is running at 2.048MHz of
> another osc. The ARM has an 18-bits of the address bus running to SRAM,
> 1-bit to the LCD controller, and 3-bits to the CS8900. The 16-bit data
> bus runs 16-bits to SRAM and the CS8900, and 8-bits to the TI Codec and
> LCD Controller. During development, SRAM will hold program code and be
> frequently accessed. The TI Codec and CS8900 will be the other two
> frequently accessed chips (VoIP application).

It's not the clock speed, so much as the speed of the pulse edges. Even if
you ran it at 1 MHz you could still have problems with poor layout. Also,
the current spikes when outputs switch can be very high, as much as 1 A,
momentarily.

>
> Should I make separate analog ground planes for the TI Codec and
> CS8900? Why do the chips have separate analog and digital grounds (AVss
> and DVss)? Can I connect these to one ground plane? If to separate
> ground planes, how should the planes connect to ground.
>
> The 5V is to power an onboard LCD the CPLD LCD controller. The 2.5V is
> the supply for the ARM core. The rest of the system is 3.3V. So I
> should make the power plane 3.3V and run 100 mil traces in the same
> layer (maybe around the edges?) for the other two supplies? How can I
> tell the auto-router to make the trace smaller as it gets closer to the
> SMT chips? Currently the auto-router tries to run 100mil traces
> straight to the SMT pins and looks like it shorts them, though that
> could simply be a visual effect. I'm using Protel DXP.

You ought to route the critical tracks like supplies and ground manually.
You can use 'fanouts' to get small tracks connecting to SMD leads. The
Protel autorouter has a very poor reputation, you'd be better off routing
all your tracks manually.

Leon

"Apparatus" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Hello,
>
> ** I feel somewhat overwhelmed by my pcb design task, so I appologize
> in advance for the length/convoluted-ness of this post. I have
> attempted to compact and clarify as best as I can.
>
> I am designing a PCB of an embedded system with mostly SMT parts. The
> board includes audio (TI TLV320AIC1106) and ethernet subsections
> (Cirrus Logic CS8900A). It also includes an Oki Semiconductor ML67Q5003
> ARM microprocessor running at 20MHz (4x PLL) clocked by a 5MHz
> oscillator. It draws not more than 0.5A, is only two layers, and has
> three regulated voltages (5, 3.3, 2.5)from a 16V 500mA wall-wart
> transformer.
>
> Using a trace width calculator at www.33each.com, I find that the 8mil
> signal traces on my board are wide enough to route power. Should I make
> them thicker (100mil?) anyway? Thicker traces confuse the Altium Situs
> auto-router around my SMT components so I would prefer not to unless
> needed.
>
> How important are ground/power planes here? Since this is a two layer
> board with close to 500 connections on the pcb, even with a 6x8" board,
> space is tight around the SMT chips, so I would like to avoid planes if
> possible. If I do add a plane, should I include dead/unconnected copper
> portions of the plane? Should planes be placed before or after
> auto-routing?
>
> What other considerations should I take? What can make routing easier?
> I've been playing with Protel DXP for a few days and was finally able
> to generate a fully routed board that I think meets manufacturing
> specs, but it was a long iterative process getting here.
>
> Does Advanced Circuits (www.33each.com) have standard hole sizes? Is it
> safe to exactly meet there minimum requirements for trace/via/pad
> separation on much of the board?

There have been lots of suggestions about going to more than 2 layers. I
would normally concur, but since this is a student project, you probably
will not have the reason or resources for that.

I disagree somewhat about splitting the ground plane. Make a logical block
diagram and the appropriate ground plane splits may become obvious. For
instance, the input power area (from you wall-wart) can be separated from
the regulated voltages. Often the dc-dc ics will be pinned out
intentionally to support this, and/or the data shets will show a recommended
layout. Also, since you have an audio section, fence off the ground for the
circuits in that area from the digital and high-speed i/o circuits. Connect
the audio ground area to the other ground at a single "gate" large enough to
support the anticipated currents. Keep the audio components over the audio
ground.

John Larkin <(E-Mail Removed)> wrote:

>
>If it's only 2 layers and has no ground plane, and power and ground
>are just skinny routed traces, I'd be astonished if it actually
>worked.

You'll be amazed what can be accomplished by using only 2 layers if
the bypass capacitors are well placed and the power is well routed. I
actually have a 2 layer 386SX 33MHz motherboard which was available
commercially (not my design, just something that ended up in a box
with PC stuff).

--
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl