Electronics Forums > FETs: measuring Vgs(off)

# FETs: measuring Vgs(off)

Paul Burridge
Guest
Posts: n/a

 09-21-2004, 03:32 PM
Hi guys,

I saw in Malvino's Electronic Principles that it is stated that Idss
and gfs (the transconductance/gain) are easy to measure, whereas
Vgs(off) is not and that manufacturers calculate it from this formula
(hope I've remembered it right)

Vgs(off) = -2*Idss/gfs

I've just checked out this assertion by measuring Vgs - v - Id for a
bunch of assorted FETs and found that I could easily establish the
pinch off voltage to within about 0.1V either way. Contrary to what
the book says, I personally have found it a simple matter to measure
Vgs(off). So why do they make out it's a big deal?

p.
--

"What is now proved was once only imagin'd." - William Blake, 1793.

Helmut Sennewald
Guest
Posts: n/a

 09-21-2004, 06:56 PM
"Paul Burridge" <(E-Mail Removed)1.co.uk> schrieb im Newsbeitrag
news:(E-Mail Removed)...
> Hi guys,
>
> I saw in Malvino's Electronic Principles that it is stated that Idss
> and gfs (the transconductance/gain) are easy to measure, whereas
> Vgs(off) is not and that manufacturers calculate it from this formula
> (hope I've remembered it right)
>
> Vgs(off) = -2*Idss/gfs
>
> I've just checked out this assertion by measuring Vgs - v - Id for a
> bunch of assorted FETs and found that I could easily establish the
> pinch off voltage to within about 0.1V either way. Contrary to what
> the book says, I personally have found it a simple matter to measure
> Vgs(off). So why do they make out it's a big deal?

Hello Paul,
Vgs_off seems to be often specified at Id=1nA. The measurement
at such low current levels takes a lot of time and it requires a
very clean test fixture.

How have you measured at exactly Id = 1nA +/-0.1nA ?

Best Regards,
Helmut

A typical datasheet:
http://www.fairchildsemi.com/ds/J3/J310.pdf

Paul Burridge
Guest
Posts: n/a

 09-21-2004, 07:30 PM
On Tue, 21 Sep 2004 20:56:00 +0200, "Helmut Sennewald"
<(E-Mail Removed)> wrote:

>Hello Paul,
>Vgs_off seems to be often specified at Id=1nA. The measurement
>at such low current levels takes a lot of time and it requires a
>very clean test fixture.
>
>How have you measured at exactly Id = 1nA +/-0.1nA ?

Hi Helmut,

Is it 1nA? I thought it was 5. No matter.
Yes, I'd expected someone to point out that the "negligible current"
point was the likely problem area. I can't honestly say that I have,
because my DVM drops out at 0.01mA! However, in the context of the
wide spread of parameters one encounters with FETs., I'm pretty
confident my 'drop-out' zone for current measurement is not too far
off the mark. But you've answered my question and as ever I'm grateful
to you for that.
I actually found it more difficult measuring Id as Vgs approached
zero. The negative tempco of these devices made that part more
challenging. Fortunately I've got a 'peak-hold' button on my meter and
by only connecting the drain circuit for a fraction of a second I was
able to get what I believe to be a valid reading. Certainly good
enough given the cushion one has to build into FET circuit design as a
matter of course, anyway.

>A typical datasheet:
>http://www.fairchildsemi.com/ds/J3/J310.pdf

Ah, I see they use a 300uS pulse, presumably to keep the device
temperature down?

Regards,

p.

John Walton
Guest
Posts: n/a

 09-21-2004, 08:05 PM
International Rectifier has a white-paper on characterizing MOSFET's --
kind of like comparing a Caterpillar D-9 to a bicycle -- but all of the
standardized measurement methods are described in detail.

If you have to measure nano, pico or femto -- Bob Pease had this interesting
article on the NatSemi website about a half-dozen years ago:

http://www.national.com/rap/Story/0,1562,5,00.html

"Paul Burridge" <(E-Mail Removed)1.co.uk> wrote in message
news:(E-Mail Removed)...
> Hi guys,
>
> I saw in Malvino's Electronic Principles that it is stated that Idss
> and gfs (the transconductance/gain) are easy to measure, whereas
> Vgs(off) is not and that manufacturers calculate it from this formula
> (hope I've remembered it right)
>
> Vgs(off) = -2*Idss/gfs
>
> I've just checked out this assertion by measuring Vgs - v - Id for a
> bunch of assorted FETs and found that I could easily establish the
> pinch off voltage to within about 0.1V either way. Contrary to what
> the book says, I personally have found it a simple matter to measure
> Vgs(off). So why do they make out it's a big deal?
>
> p.
> --
>
> "What is now proved was once only imagin'd." - William Blake, 1793.

Ian Stirling
Guest
Posts: n/a

 09-22-2004, 12:19 AM
In sci.electronics.design Paul Burridge <(E-Mail Removed)1.co.uk> wrote:
> On Tue, 21 Sep 2004 20:56:00 +0200, "Helmut Sennewald"
> <(E-Mail Removed)> wrote:
>
>>Hello Paul,
>>Vgs_off seems to be often specified at Id=1nA. The measurement
>>at such low current levels takes a lot of time and it requires a
>>very clean test fixture.
>>
>>How have you measured at exactly Id = 1nA +/-0.1nA ?

>
> Hi Helmut,
>
> Is it 1nA? I thought it was 5. No matter.
> Yes, I'd expected someone to point out that the "negligible current"
> point was the likely problem area. I can't honestly say that I have,
> because my DVM drops out at 0.01mA! However, in the context of the

Turn it to voltage.
Most meters (the four I've measured) have a 1Mohm or so input impedance
on the 200mv range.
This is 200nA full scale.
Probably best to do the test twice, with the meter leads reversed though.

Winfield Hill
Guest
Posts: n/a

 09-22-2004, 02:50 AM
Ian Stirling wrote...
>
> Paul Burridge wrote:
>> Helmut Sennewald wrote:
>>
>>> Vgs_off seems to be often specified at Id=1nA. The measurement
>>> at such low current levels takes a lot of time and it requires a
>>> very clean test fixture.

>>
>> Is it 1nA? I thought it was 5. No matter.
>> Yes, I'd expected someone to point out that the "negligible current"
>> point was the likely problem area. I can't honestly say that I have,
>> because my DVM drops out at 0.01mA! However, in the context of the

>
> Turn it to voltage. Most meters (the four I've measured) have a 1Mohm
> or so input impedance on the 200mv range. This is 200nA full scale.
> Probably best to do the test twice, with the meter leads reversed though.

The multimeters on my bench have infinite input impedance on the 200mV
scale, although some let you turn on an internal resistor. We can use
external 10M or 100M if we like, which gives 1pA and 0.1pA measurement
resolution with a 4.5-digit meter.

The relevant "subthreshold" formula is Id = k e^(Vgs - Vt), which is
an exponential equation that clearly shows there's no sudden threshold
for FET current => negligible. Paul can take a look at AoE page 123,
and observe the measured gate-voltage to drain current relationship for
a typical MOSFET, which shows the standard smooth 100 or 150mV/decade
(p or n-type) gate-voltage change over a wide 7-decade current range.

1 or 5nA makes no difference? Nope, that apparently small detail makes
a predictably large 70 to 100mV difference. One must pay attention to
the specifications in this matter, 1nA, 1uA, whatever - it's a big deal.

BTW, as I've pointed out several times, power MOSFET spice models are
completely wrong in this region, just forget considering their results.

--
Thanks,
- Win

(email: use hill_at_rowland-dotties-org for now)

Paul Burridge
Guest
Posts: n/a

 09-22-2004, 04:47 PM
Thanks, all, BTW.

On 21 Sep 2004 19:50:22 -0700, Winfield Hill
<(E-Mail Removed)> wrote:

> The multimeters on my bench have infinite input impedance on the 200mV
> scale, although some let you turn on an internal resistor. We can use
> external 10M or 100M if we like, which gives 1pA and 0.1pA measurement
> resolution with a 4.5-digit meter.

I admit I never thought of doing it this way. Incidentally, talking of
very low currents, on P.170 you've reproduced a picture of a static
damaged MOSFET. I assume from the commentary that this one was totally
trashed, but you've stated before that these devices can be partially
blown and still function, albeit to an impaired extent. Could one
feasibly measure any such 'minor damage' (through static) by checking
for picoamp range current leakage across the insulating layer?

> The relevant "subthreshold" formula is Id = k e^(Vgs - Vt), which is
> an exponential equation that clearly shows there's no sudden threshold
> for FET current => negligible. Paul can take a look at AoE page 123,
> and observe the measured gate-voltage to drain current relationship for
> a typical MOSFET, which shows the standard smooth 100 or 150mV/decade
> (p or n-type) gate-voltage change over a wide 7-decade current range.
>
> 1 or 5nA makes no difference? Nope, that apparently small detail makes
> a predictably large 70 to 100mV difference. One must pay attention to
> the specifications in this matter, 1nA, 1uA, whatever - it's a big deal.

Oh bugger.
>
> BTW, as I've pointed out several times, power MOSFET spice models are
> completely wrong in this region, just forget considering their results.

Yes, I think the same caveat applies for simulating FETs - and that's
just in the active region!

--

"What is now proved was once only imagin'd." - William Blake, 1793.

Tony Williams
Guest
Posts: n/a

 09-23-2004, 09:10 AM
In article <(E-Mail Removed)>,
Paul Burridge <(E-Mail Removed)1.co.uk> wrote:

> Yes, I'd expected someone to point out that the "negligible
> current" point was the likely problem area. I can't honestly say
> that I have, because my DVM drops out at 0.01mA! However, in the
> context of the wide spread of parameters one encounters with
> FETs., I'm pretty confident my 'drop-out' zone for current
> measurement is not too far off the mark. But you've answered my
> question and as ever I'm grateful to you for that. I actually
> found it more difficult measuring Id as Vgs approached zero.

[snip]

Paul, you might try the belt 'n braces method.

--+--+15v
|
|--+
+--->|
| |--+
| |
| +------->To DVM
| |
| \
| /R
| \
| |
0v--+-------+------->

Self-bias the jfet with resistor R, and measure the
voltage across it. This gives you the Vgs and Id.

Use two values of R, say 1k and 5k, and plug the
results into the Id = Idss(etc) equation. Solve the
two equations for Idss and Vgs(off).

You've been wandering around this problem for days now.
It might help if you could get hold of an old Siliconix
Technical Article, TA70-2, first published in Electronics
Design in May 1970, then included in the App Notes at the
rear of most Siliconix FET data books for the next 15 or
20 years thereafter.

TA70-2 shows you how to plot Id/Vgs and gfs/Vgs curves
and use them to determine the best bias point for minimum
Id and gfs variations.

--
Tony Williams.

Winfield Hill
Guest
Posts: n/a

 09-23-2004, 10:18 AM
Tony Williams wrote...
>
> Paul Burridge <(E-Mail Removed)1.co.uk> wrote:
>
>> Yes, I'd expected someone to point out that the "negligible
>> current" point was the likely problem area. I can't honestly say
>> that I have, because my DVM drops out at 0.01mA! However, in the
>> context of the wide spread of parameters one encounters with
>> FETs., I'm pretty confident my 'drop-out' zone for current
>> measurement is not too far off the mark. But you've answered my
>> question and as ever I'm grateful to you for that. I actually
>> found it more difficult measuring Id as Vgs approached zero.

>[snip]
>
> Paul, you might try the belt 'n braces method.
>
> --+--+15v
> |
> |--+
> +--->|
> | |--+
> | |
> | +------->To DVM
> | |
> | \
> | /R
> | \
> | |
> 0v--+-------+------->
>
> Self-bias the jfet with resistor R, and measure the
> voltage across it. This gives you the Vgs and Id.
>
> Use two values of R, say 1k and 5k, and plug the
> results into the Id = Idss(etc) equation. Solve the
> two equations for Idss and Vgs(off).
>
> You've been wandering around this problem for days now.
> It might help if you could get hold of an old Siliconix
> Technical Article, TA70-2, first published in Electronics
> Design in May 1970, then included in the App Notes at the
> rear of most Siliconix FET data books for the next 15 or
> 20 years thereafter.
>
> TA70-2 shows you how to plot Id/Vgs and gfs/Vgs curves
> and use them to determine the best bias point for minimum
> Id and gfs variations.

Tony, now found as Vishay's AN102 (Siliconix, 10-Mar-97)?
See http://www.vishay.com/docs/70595/70595.pdf

--
Thanks,
- Win

(email: use hill_at_rowland-dotties-org for now)

Winfield Hill
Guest
Posts: n/a

 09-23-2004, 10:21 AM
Tony Williams wrote...
>
> It might help if you could get hold of an old Siliconix
> Technical Article, TA70-2, first published in Electronics
> Design in May 1970, then included in the App Notes at the
> rear of most Siliconix FET data books for the next 15 or
> 20 years thereafter.

Tony, if you have access to the May 1970 ED article, do you
know who the author was? Also, was the Siliconix app note
substantially the same?

--
Thanks,
- Win

(email: use hill_at_rowland-dotties-org for now)

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