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# CMOS inverter dynamic behavior!

Francesco
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 06-23-2006, 04:20 PM
I'm studyng CMOS inverter dynamic behavior, and in my book I read at
first that the two transistor NMOS and PMOS ohw compose the inverter are
forbidden or in saturation for all the first half of the logical
excursion (until the 50%)

I think that ,for example if at the output I have logic level H (VDD)
and I turn on the NMOS, it is in saturation until VDS>=VDD-VT (VT is the
threshold voltage), then it go on linear mode.

Obviously the same situation for the PMOS in the L-->H excursion.

What I don't understand?

Sorry for my english!

Francesco

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KodKodKod Learning Consulting
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 06-24-2006, 11:01 PM
Hi Francesco,

This is how we would describe the CMOS inverter switching behavior.

Assume at the beginning, the input is at 0V. (Vin = 0V). As it
increases,

when Vin < Vthn, NMOS is off. And PMOS is ON. So the Vout is Vdd. This
means that the PMOS is in linear region.

When Vin> Vthn, NMOS is ON. And Vout decreases. Since Vout is still
high, NMOS is in saturation region. At the beginning, PMOS is still in
linear region. But as Vin increases more and Vout decreases more, there
is a point that PMOS will go into saturation region. And there is
another point NMOS will go into linear region (because Vout will be so
low that Vin-Vout=Vgate-Vdrain>Vth).

Eventually, when Vin is > Vdd - |Vthp|, PMOS is off and NMOS is in
linear region. Now, the Vout = 0V.

In short, as Vin changes from 0V to VDD: PMOS: Linear => Sat = >OFF,
and NMOS: OFF=>sat=>Linear

And at 50% point, since Vin=Vout, (That means Vg = Vd for both NMOS and
PMOS), both are at saturation region.

Send us an email if you need more explanation.

KodKodKod Learning Consulting
http://www.kodkodkod.com

Francesco wrote:
> I'm studyng CMOS inverter dynamic behavior, and in my book I read at
> first that the two transistor NMOS and PMOS ohw compose the inverter are
> forbidden or in saturation for all the first half of the logical
> excursion (until the 50%)
>
> I think that ,for example if at the output I have logic level H (VDD)
> and I turn on the NMOS, it is in saturation until VDS>=VDD-VT (VT is the
> threshold voltage), then it go on linear mode.
>
> Obviously the same situation for the PMOS in the L-->H excursion.
>
> What I don't understand?
>
> Sorry for my english!
>
> Francesco
>
> --
> To answer me remove the numbers!

Francesco
Guest
Posts: n/a

 06-25-2006, 06:33 AM
KodKodKod Learning Consulting ha scritto:
_cut_
> And at 50% point, since Vin=Vout, (That means Vg = Vd for both NMOS and
> PMOS), both are at saturation region.

I agree this, but before the 50% point, has you see, then two MOS aren't
in saturation! I'wrong? Why?

Can you explain me the case of Vin as an ideal current generator!

Thank's for your patience, and once more sorry for my english!

Francesco

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